Formal Verification of Descriptions with Distinct Order of Memory Operations

Formal veriication tools must often cope with large memory sizes and indirect addressing. This paper presents a new approach of how to handle memory operations in the symbolic simulation of designs with complex control logic, e.g., processors. The simulator is currently used to check the equivalence of two processor descriptions with distinct order of memory operations. During symbolic simulation, relationships between memory operations are automatically detected while addresses and the memory states are given symbolically to summarize many test-vectors. The integration of the technique in the equivalence checker is demonstrated by example designs.